In general, high-voltage integrated circuits in which at least one high-voltage transistor is arranged on the same chip together with low voltage circuits are widely used in a variety of electrical applications. In these circuits, a LDMOS transistor is an important high voltage device. FIG. 1 is a diagrammatic view of a typical LDMOS device showing a flux tube and impact ionization zones of the device. As shown, LDMOS device 10 includes a P substrate 12, an nwell layer 14, n+ drain 16, p body 18, n+ source 20 diffused in p body 18, P+ tap 19, source contact 22, and drain contact 24. A gate 26 overlies source 20 and p body 18 and is located between source 20 and drain 16. A flux tube 28 extends between drain 16 and source 20 and forms a surface channel under gate 26. Impact ionization zones 30 and 32 are located along tube 28 at drain 16 and at p body 18 at areas 34 and 36, respectively, of the drift region. FIG. 2 is a graphical illustration of the surface E-field for the device of FIG. 1. The surface E-field 38 has peaks 40 and 42 of drift region ND and a plateau 44 between peaks 40, 42.
In order improve a high voltage LDMOS device, it is desirable to cut the surface E-field peaks and to lower the surface E-field. As an example, in order to meet the global requirements of a high voltage device where VRMS can be 110V to 277V, the Vpeak can be 186V to 470v and a voltage spike can be 336V to 620V, the device desirably should have a breakdown voltage of 700V.
U.S. Pat. No. 6,097,063, issued Apr. 1, 2000, inventor Fujihira, is of interest and discloses a semiconductor device which has a drift region in which current flows if it is in the on mode and which is depleted if it is in the off mode. The drift region is formed as a structure having a plurality of first conductive type drift regions and a plurality of a second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions respectively. The disclosed device is disadvantageous in the number of process steps required to make the device.
There is thus a need for a high voltage LDMOS device which has reduced surface E-field and E-field peaks, a reduced on resistance, reduced device size, and a simplified process for making the device.